SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiDualPortRam Entity Reference
axi
+ Inheritance diagram for AxiDualPortRam:
+ Collaboration diagram for AxiDualPortRam:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
BRAM_EN_G  boolean := false
REG_EN_G  boolean := true
MODE_G  string := " read-first "
AXI_WR_EN_G  boolean := true
SYS_WR_EN_G  boolean := false
SYS_BYTE_WR_EN_G  boolean := false
COMMON_CLK_G  boolean := false
ADDR_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 5
DATA_WIDTH_G  integer := 32
INIT_G  slv := " 0 "
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C

Ports

axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
clk   in sl := ' 0 '
en   in sl := ' 1 '
we   in sl := ' 0 '
weByte   in slv ( wordCount ( DATA_WIDTH_G , 8 ) - 1 downto 0 ) := ( others = > ' 0 ' )
rst   in sl := ' 0 '
addr   in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
din   in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
dout   out slv ( DATA_WIDTH_G - 1 downto 0 )
axiWrValid   out sl
axiWrStrobe   out slv ( wordCount ( DATA_WIDTH_G , 8 ) - 1 downto 0 )
axiWrAddr   out slv ( ADDR_WIDTH_G - 1 downto 0 )
axiWrData   out slv ( DATA_WIDTH_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 29 of file AxiDualPortRam.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file AxiDualPortRam.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := false
Generic

Definition at line 33 of file AxiDualPortRam.vhd.

◆ REG_EN_G

REG_EN_G boolean := true
Generic

Definition at line 34 of file AxiDualPortRam.vhd.

◆ MODE_G

MODE_G string := " read-first "
Generic

Definition at line 35 of file AxiDualPortRam.vhd.

◆ AXI_WR_EN_G

AXI_WR_EN_G boolean := true
Generic

Definition at line 36 of file AxiDualPortRam.vhd.

◆ SYS_WR_EN_G

SYS_WR_EN_G boolean := false
Generic

Definition at line 37 of file AxiDualPortRam.vhd.

◆ SYS_BYTE_WR_EN_G

SYS_BYTE_WR_EN_G boolean := false
Generic

Definition at line 38 of file AxiDualPortRam.vhd.

◆ COMMON_CLK_G

COMMON_CLK_G boolean := false
Generic

Definition at line 39 of file AxiDualPortRam.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G integer range 1 to ( 2 ** 24 ) := 5
Generic

Definition at line 40 of file AxiDualPortRam.vhd.

◆ DATA_WIDTH_G

DATA_WIDTH_G integer := 32
Generic

Definition at line 41 of file AxiDualPortRam.vhd.

◆ INIT_G

INIT_G slv := " 0 "
Generic

Definition at line 42 of file AxiDualPortRam.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 43 of file AxiDualPortRam.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 47 of file AxiDualPortRam.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 48 of file AxiDualPortRam.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 49 of file AxiDualPortRam.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 50 of file AxiDualPortRam.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 51 of file AxiDualPortRam.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 52 of file AxiDualPortRam.vhd.

◆ clk

clk in sl := ' 0 '
Port

Definition at line 55 of file AxiDualPortRam.vhd.

◆ en

en in sl := ' 1 '
Port

Definition at line 56 of file AxiDualPortRam.vhd.

◆ we

we in sl := ' 0 '
Port

Definition at line 57 of file AxiDualPortRam.vhd.

◆ weByte

weByte in slv ( wordCount ( DATA_WIDTH_G , 8 ) - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 58 of file AxiDualPortRam.vhd.

◆ rst

rst in sl := ' 0 '
Port

Definition at line 59 of file AxiDualPortRam.vhd.

◆ addr

addr in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 60 of file AxiDualPortRam.vhd.

◆ din

din in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 61 of file AxiDualPortRam.vhd.

◆ dout

dout out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 62 of file AxiDualPortRam.vhd.

◆ axiWrValid

axiWrValid out sl
Port

Definition at line 63 of file AxiDualPortRam.vhd.

◆ axiWrStrobe

axiWrStrobe out slv ( wordCount ( DATA_WIDTH_G , 8 ) - 1 downto 0 )
Port

Definition at line 64 of file AxiDualPortRam.vhd.

◆ axiWrAddr

axiWrAddr out slv ( ADDR_WIDTH_G - 1 downto 0 )
Port

Definition at line 65 of file AxiDualPortRam.vhd.

◆ axiWrData

axiWrData out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 66 of file AxiDualPortRam.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file AxiDualPortRam.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file AxiDualPortRam.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiDualPortRam.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 22 of file AxiDualPortRam.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file AxiDualPortRam.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 25 of file AxiDualPortRam.vhd.

The documentation for this class was generated from the following file: