SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiDac7654Core Entity Reference
devices » Ti » dac7654
+ Inheritance diagram for AxiDac7654Core:
+ Collaboration diagram for AxiDac7654Core:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiDac7654Pkg  Package <AxiDac7654Pkg>

Generics

TPD_G  time := 1 ns
AXI_CLK_FREQ_G  real := 125 . 0E + 6
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

dacIn   in AxiDac7654InType
dacOut   out AxiDac7654OutType
axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 27 of file AxiDac7654Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file AxiDac7654Core.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 125 . 0E + 6
Generic

Definition at line 30 of file AxiDac7654Core.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 31 of file AxiDac7654Core.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 32 of file AxiDac7654Core.vhd.

◆ dacIn

dacIn in AxiDac7654InType
Port

Definition at line 35 of file AxiDac7654Core.vhd.

◆ dacOut

dacOut out AxiDac7654OutType
Port

Definition at line 36 of file AxiDac7654Core.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 38 of file AxiDac7654Core.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 39 of file AxiDac7654Core.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 40 of file AxiDac7654Core.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 41 of file AxiDac7654Core.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 42 of file AxiDac7654Core.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 43 of file AxiDac7654Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiDac7654Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiDac7654Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file AxiDac7654Core.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 22 of file AxiDac7654Core.vhd.

◆ AxiDac7654Pkg

AxiDac7654Pkg
Package

Definition at line 23 of file AxiDac7654Core.vhd.

The documentation for this class was generated from the following file: