SURF  1.0
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AxiAds42lb69Reg Entity Reference
devices » Ti » ads42lb69
+ Inheritance diagram for AxiAds42lb69Reg:
+ Collaboration diagram for AxiAds42lb69Reg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiAds42lb69Pkg  Package <AxiAds42lb69Pkg>

Generics

TPD_G  time := 1 ns
SIM_SPEEDUP_G  boolean := false
ADC_CLK_FREQ_G  real := 250 . 00E + 6
DMODE_INIT_G  slv ( 1 downto 0 ) := " 00 "
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
status   in AxiAds42lb69StatusType
config   out AxiAds42lb69ConfigType
adcClk   in sl
adcRst   in sl
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 29 of file AxiAds42lb69Reg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiAds42lb69Reg.vhd.

◆ SIM_SPEEDUP_G

SIM_SPEEDUP_G boolean := false
Generic

Definition at line 32 of file AxiAds42lb69Reg.vhd.

◆ ADC_CLK_FREQ_G

ADC_CLK_FREQ_G real := 250 . 00E + 6
Generic

Definition at line 33 of file AxiAds42lb69Reg.vhd.

◆ DMODE_INIT_G

DMODE_INIT_G slv ( 1 downto 0 ) := " 00 "
Generic

Definition at line 34 of file AxiAds42lb69Reg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 35 of file AxiAds42lb69Reg.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 38 of file AxiAds42lb69Reg.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 39 of file AxiAds42lb69Reg.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 40 of file AxiAds42lb69Reg.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 41 of file AxiAds42lb69Reg.vhd.

◆ status

status in AxiAds42lb69StatusType
Port

Definition at line 43 of file AxiAds42lb69Reg.vhd.

◆ config

config out AxiAds42lb69ConfigType
Port

Definition at line 44 of file AxiAds42lb69Reg.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 46 of file AxiAds42lb69Reg.vhd.

◆ adcRst

adcRst in sl
Port

Definition at line 47 of file AxiAds42lb69Reg.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 48 of file AxiAds42lb69Reg.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 50 of file AxiAds42lb69Reg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAds42lb69Reg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAds42lb69Reg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiAds42lb69Reg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiAds42lb69Reg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiAds42lb69Reg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiAds42lb69Reg.vhd.

◆ AxiAds42lb69Pkg

AxiAds42lb69Pkg
Package

Definition at line 25 of file AxiAds42lb69Reg.vhd.

The documentation for this class was generated from the following file: