SURF  1.0
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AxiAds42lb69Core Entity Reference
devices » Ti » ads42lb69
+ Inheritance diagram for AxiAds42lb69Core:
+ Collaboration diagram for AxiAds42lb69Core:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiAds42lb69Pkg  Package <AxiAds42lb69Pkg>

Generics

TPD_G  time := 1 ns
SIM_SPEEDUP_G  boolean := false
USE_PLL_G  boolean := false
ADC_CLK_FREQ_G  real := 250 . 00E + 6
DMODE_INIT_G  slv ( 1 downto 0 ) := " 00 "
DELAY_INIT_G  Slv9VectorArray ( 1 downto 0 , 7 downto 0 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
IODELAY_GROUP_G  string := " AXI_ADS42LB69_IODELAY_GRP "
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
XIL_DEVICE_G  string := " 7SERIES "

Ports

adcIn   in AxiAds42lb69InType
adcOut   out AxiAds42lb69OutType
adcSync   in sl
adcData   out Slv16Array ( 1 downto 0 )
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl
adcClk   in sl
adcRst   in sl
refclk200MHz   in sl

Detailed Description

See also
entity

Definition at line 27 of file AxiAds42lb69Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file AxiAds42lb69Core.vhd.

◆ SIM_SPEEDUP_G

SIM_SPEEDUP_G boolean := false
Generic

Definition at line 30 of file AxiAds42lb69Core.vhd.

◆ USE_PLL_G

USE_PLL_G boolean := false
Generic

Definition at line 31 of file AxiAds42lb69Core.vhd.

◆ ADC_CLK_FREQ_G

ADC_CLK_FREQ_G real := 250 . 00E + 6
Generic

Definition at line 32 of file AxiAds42lb69Core.vhd.

◆ DMODE_INIT_G

DMODE_INIT_G slv ( 1 downto 0 ) := " 00 "
Generic

Definition at line 33 of file AxiAds42lb69Core.vhd.

◆ DELAY_INIT_G

DELAY_INIT_G Slv9VectorArray ( 1 downto 0 , 7 downto 0 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
Generic

Definition at line 34 of file AxiAds42lb69Core.vhd.

◆ IODELAY_GROUP_G

IODELAY_GROUP_G string := " AXI_ADS42LB69_IODELAY_GRP "
Generic

Definition at line 35 of file AxiAds42lb69Core.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 36 of file AxiAds42lb69Core.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 37 of file AxiAds42lb69Core.vhd.

◆ adcIn

adcIn in AxiAds42lb69InType
Port

Definition at line 40 of file AxiAds42lb69Core.vhd.

◆ adcOut

adcOut out AxiAds42lb69OutType
Port

Definition at line 41 of file AxiAds42lb69Core.vhd.

◆ adcSync

adcSync in sl
Port

Definition at line 43 of file AxiAds42lb69Core.vhd.

◆ adcData

adcData out Slv16Array ( 1 downto 0 )
Port

Definition at line 44 of file AxiAds42lb69Core.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 46 of file AxiAds42lb69Core.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 47 of file AxiAds42lb69Core.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 48 of file AxiAds42lb69Core.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 49 of file AxiAds42lb69Core.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 51 of file AxiAds42lb69Core.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 52 of file AxiAds42lb69Core.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 53 of file AxiAds42lb69Core.vhd.

◆ adcRst

adcRst in sl
Port

Definition at line 54 of file AxiAds42lb69Core.vhd.

◆ refclk200MHz

refclk200MHz in sl
Port

Definition at line 55 of file AxiAds42lb69Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAds42lb69Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAds42lb69Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file AxiAds42lb69Core.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 22 of file AxiAds42lb69Core.vhd.

◆ AxiAds42lb69Pkg

AxiAds42lb69Pkg
Package

Definition at line 23 of file AxiAds42lb69Core.vhd.

The documentation for this class was generated from the following file: