SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiAd9467Reg Entity Reference
devices » AnalogDevices » ad9467
+ Inheritance diagram for AxiAd9467Reg:
+ Collaboration diagram for AxiAd9467Reg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiAd9467Pkg  Package <AxiAd9467Pkg>

Generics

TPD_G  time := 1 ns
DEMUX_INIT_G  sl := ' 0 '
DELAY_INIT_G  Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
status   in AxiAd9467StatusType
config   out AxiAd9467ConfigType
adcClk   in sl
adcRst   in sl
refClk200MHz   in sl

Detailed Description

See also
entity

Definition at line 29 of file AxiAd9467Reg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiAd9467Reg.vhd.

◆ DEMUX_INIT_G

DEMUX_INIT_G sl := ' 0 '
Generic

Definition at line 32 of file AxiAd9467Reg.vhd.

◆ DELAY_INIT_G

DELAY_INIT_G Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
Generic

Definition at line 33 of file AxiAd9467Reg.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 34 of file AxiAd9467Reg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 35 of file AxiAd9467Reg.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 38 of file AxiAd9467Reg.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 39 of file AxiAd9467Reg.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 40 of file AxiAd9467Reg.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 41 of file AxiAd9467Reg.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 42 of file AxiAd9467Reg.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 43 of file AxiAd9467Reg.vhd.

◆ status

status in AxiAd9467StatusType
Port

Definition at line 45 of file AxiAd9467Reg.vhd.

◆ config

config out AxiAd9467ConfigType
Port

Definition at line 46 of file AxiAd9467Reg.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 48 of file AxiAd9467Reg.vhd.

◆ adcRst

adcRst in sl
Port

Definition at line 49 of file AxiAd9467Reg.vhd.

◆ refClk200MHz

refClk200MHz in sl
Port

Definition at line 50 of file AxiAd9467Reg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAd9467Reg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAd9467Reg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiAd9467Reg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiAd9467Reg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiAd9467Reg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiAd9467Reg.vhd.

◆ AxiAd9467Pkg

AxiAd9467Pkg
Package

Definition at line 25 of file AxiAd9467Reg.vhd.

The documentation for this class was generated from the following file: