SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiAd9467Pll Entity Reference
devices » AnalogDevices » ad9467
+ Inheritance diagram for AxiAd9467Pll:
+ Collaboration diagram for AxiAd9467Pll:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
ADC_CLK_FREQ_G  real := 250 . 0E + 6

Ports

adcClkOutP   out sl
adcClkOutN   out sl
adcClkInP   in sl
adcClkInN   in sl
pllLocked   out sl
adcClk   in sl
adcRst   in sl

Detailed Description

See also
entity

Definition at line 28 of file AxiAd9467Pll.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file AxiAd9467Pll.vhd.

◆ ADC_CLK_FREQ_G

ADC_CLK_FREQ_G real := 250 . 0E + 6
Generic

Definition at line 31 of file AxiAd9467Pll.vhd.

◆ adcClkOutP

adcClkOutP out sl
Port

Definition at line 34 of file AxiAd9467Pll.vhd.

◆ adcClkOutN

adcClkOutN out sl
Port

Definition at line 35 of file AxiAd9467Pll.vhd.

◆ adcClkInP

adcClkInP in sl
Port

Definition at line 36 of file AxiAd9467Pll.vhd.

◆ adcClkInN

adcClkInN in sl
Port

Definition at line 37 of file AxiAd9467Pll.vhd.

◆ pllLocked

pllLocked out sl
Port

Definition at line 39 of file AxiAd9467Pll.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 41 of file AxiAd9467Pll.vhd.

◆ adcRst

adcRst in sl
Port

Definition at line 42 of file AxiAd9467Pll.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAd9467Pll.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAd9467Pll.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file AxiAd9467Pll.vhd.

◆ unisim

unisim
Library

Definition at line 23 of file AxiAd9467Pll.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 24 of file AxiAd9467Pll.vhd.

The documentation for this class was generated from the following file: