SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiAd9467Mon Entity Reference
devices » AnalogDevices » ad9467
+ Inheritance diagram for AxiAd9467Mon:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
ADC_CLK_FREQ_G  real := 250 . 0E + 6

Ports

adcClk   in sl
adcRst   in sl
adcData   in slv ( 15 downto 0 )
adcDataMon   out Slv16Array ( 0 to 15 )

Detailed Description

See also
entity

Definition at line 27 of file AxiAd9467Mon.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file AxiAd9467Mon.vhd.

◆ ADC_CLK_FREQ_G

ADC_CLK_FREQ_G real := 250 . 0E + 6
Generic

Definition at line 30 of file AxiAd9467Mon.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 32 of file AxiAd9467Mon.vhd.

◆ adcRst

adcRst in sl
Port

Definition at line 33 of file AxiAd9467Mon.vhd.

◆ adcData

adcData in slv ( 15 downto 0 )
Port

Definition at line 34 of file AxiAd9467Mon.vhd.

◆ adcDataMon

adcDataMon out Slv16Array ( 0 to 15 )
Port

Definition at line 35 of file AxiAd9467Mon.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAd9467Mon.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAd9467Mon.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiAd9467Mon.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiAd9467Mon.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiAd9467Mon.vhd.

The documentation for this class was generated from the following file: