SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiAd9467Deser Entity Reference
devices » AnalogDevices » ad9467
+ Inheritance diagram for AxiAd9467Deser:
+ Collaboration diagram for AxiAd9467Deser:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiAd9467Pkg  Package <AxiAd9467Pkg>
vcomponents 

Generics

TPD_G  time := 1 ns
DELAY_INIT_G  Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
IODELAY_GROUP_G  string := " AXI_AD9467_IODELAY_GRP "

Ports

adcDataOrP   in sl
adcDataOrN   in sl
adcDataInP   in slv ( 7 downto 0 )
adcDataInN   in slv ( 7 downto 0 )
adcClk   in sl
adcRst   in sl
adcData   out slv ( 15 downto 0 )
refClk200Mhz   in sl
delayin   in AxiAd9467DelayInType
delayOut   out AxiAd9467DelayOutType

Detailed Description

See also
entity

Definition at line 31 of file AxiAd9467Deser.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file AxiAd9467Deser.vhd.

◆ DELAY_INIT_G

DELAY_INIT_G Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
Generic

Definition at line 34 of file AxiAd9467Deser.vhd.

◆ IODELAY_GROUP_G

IODELAY_GROUP_G string := " AXI_AD9467_IODELAY_GRP "
Generic

Definition at line 35 of file AxiAd9467Deser.vhd.

◆ adcDataOrP

adcDataOrP in sl
Port

Definition at line 38 of file AxiAd9467Deser.vhd.

◆ adcDataOrN

adcDataOrN in sl
Port

Definition at line 39 of file AxiAd9467Deser.vhd.

◆ adcDataInP

adcDataInP in slv ( 7 downto 0 )
Port

Definition at line 40 of file AxiAd9467Deser.vhd.

◆ adcDataInN

adcDataInN in slv ( 7 downto 0 )
Port

Definition at line 41 of file AxiAd9467Deser.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 43 of file AxiAd9467Deser.vhd.

◆ adcRst

adcRst in sl
Port

Definition at line 44 of file AxiAd9467Deser.vhd.

◆ adcData

adcData out slv ( 15 downto 0 )
Port

Definition at line 45 of file AxiAd9467Deser.vhd.

◆ refClk200Mhz

refClk200Mhz in sl
Port

Definition at line 47 of file AxiAd9467Deser.vhd.

◆ delayin

delayin in AxiAd9467DelayInType
Port

Definition at line 48 of file AxiAd9467Deser.vhd.

◆ delayOut

delayOut out AxiAd9467DelayOutType
Port

Definition at line 49 of file AxiAd9467Deser.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAd9467Deser.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAd9467Deser.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiAd9467Deser.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiAd9467Deser.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiAd9467Deser.vhd.

◆ AxiAd9467Pkg

AxiAd9467Pkg
Package

Definition at line 24 of file AxiAd9467Deser.vhd.

◆ unisim

unisim
Library

Definition at line 26 of file AxiAd9467Deser.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 27 of file AxiAd9467Deser.vhd.

The documentation for this class was generated from the following file: