SURF  1.0
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AxiAd9467Core Entity Reference
devices » AnalogDevices » ad9467
+ Inheritance diagram for AxiAd9467Core:
+ Collaboration diagram for AxiAd9467Core:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiAd9467Pkg  Package <AxiAd9467Pkg>

Generics

TPD_G  time := 1 ns
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
AXI_CLK_FREQ_G  real := 125 . 0E + 6
ADC_CLK_FREQ_G  real := 250 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
DEMUX_INIT_G  sl := ' 0 '
DELAY_INIT_G  Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
IODELAY_GROUP_G  string := " AXI_AD9467_IODELAY_GRP "

Ports

adcIn   in AxiAd9467InType
adcInOut   inout AxiAd9467InOutType
adcOut   out AxiAd9467OutType
adcClk   in sl
adcRst   in sl
adcData   out slv ( 15 downto 0 )
refClk200Mhz   in sl
axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 27 of file AxiAd9467Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file AxiAd9467Core.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 30 of file AxiAd9467Core.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 125 . 0E + 6
Generic

Definition at line 31 of file AxiAd9467Core.vhd.

◆ ADC_CLK_FREQ_G

ADC_CLK_FREQ_G real := 250 . 0E + 6
Generic

Definition at line 32 of file AxiAd9467Core.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 33 of file AxiAd9467Core.vhd.

◆ DEMUX_INIT_G

DEMUX_INIT_G sl := ' 0 '
Generic

Definition at line 34 of file AxiAd9467Core.vhd.

◆ DELAY_INIT_G

DELAY_INIT_G Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
Generic

Definition at line 35 of file AxiAd9467Core.vhd.

◆ IODELAY_GROUP_G

IODELAY_GROUP_G string := " AXI_AD9467_IODELAY_GRP "
Generic

Definition at line 36 of file AxiAd9467Core.vhd.

◆ adcIn

adcIn in AxiAd9467InType
Port

Definition at line 39 of file AxiAd9467Core.vhd.

◆ adcInOut

adcInOut inout AxiAd9467InOutType
Port

Definition at line 40 of file AxiAd9467Core.vhd.

◆ adcOut

adcOut out AxiAd9467OutType
Port

Definition at line 41 of file AxiAd9467Core.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 43 of file AxiAd9467Core.vhd.

◆ adcRst

adcRst in sl
Port

Definition at line 44 of file AxiAd9467Core.vhd.

◆ adcData

adcData out slv ( 15 downto 0 )
Port

Definition at line 45 of file AxiAd9467Core.vhd.

◆ refClk200Mhz

refClk200Mhz in sl
Port

Definition at line 47 of file AxiAd9467Core.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 49 of file AxiAd9467Core.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 50 of file AxiAd9467Core.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 51 of file AxiAd9467Core.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 52 of file AxiAd9467Core.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 53 of file AxiAd9467Core.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 54 of file AxiAd9467Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAd9467Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAd9467Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file AxiAd9467Core.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 22 of file AxiAd9467Core.vhd.

◆ AxiAd9467Pkg

AxiAd9467Pkg
Package

Definition at line 23 of file AxiAd9467Core.vhd.

The documentation for this class was generated from the following file: