SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiAd5780Reg Entity Reference
devices » AnalogDevices » ad5780
+ Inheritance diagram for AxiAd5780Reg:
+ Collaboration diagram for AxiAd5780Reg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiAd5780Pkg  Package <AxiAd5780Pkg>

Generics

TPD_G  time := 1 ns
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
USE_DSP48_G  string := " no "
AXI_CLK_FREQ_G  real := 200 . 0E + 6
SPI_CLK_FREQ_G  real := 25 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
status   in AxiAd5780StatusType
config   out AxiAd5780ConfigType
axiClk   in sl
axiRst   in sl
dacRst   out sl

Detailed Description

See also
entity

Definition at line 29 of file AxiAd5780Reg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiAd5780Reg.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 32 of file AxiAd5780Reg.vhd.

◆ USE_DSP48_G

USE_DSP48_G string := " no "
Generic

Definition at line 33 of file AxiAd5780Reg.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 34 of file AxiAd5780Reg.vhd.

◆ SPI_CLK_FREQ_G

SPI_CLK_FREQ_G real := 25 . 0E + 6
Generic

Definition at line 35 of file AxiAd5780Reg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 36 of file AxiAd5780Reg.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 39 of file AxiAd5780Reg.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 40 of file AxiAd5780Reg.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 41 of file AxiAd5780Reg.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 42 of file AxiAd5780Reg.vhd.

◆ status

status in AxiAd5780StatusType
Port

Definition at line 44 of file AxiAd5780Reg.vhd.

◆ config

config out AxiAd5780ConfigType
Port

Definition at line 45 of file AxiAd5780Reg.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 47 of file AxiAd5780Reg.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 48 of file AxiAd5780Reg.vhd.

◆ dacRst

dacRst out sl
Port

Definition at line 49 of file AxiAd5780Reg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAd5780Reg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAd5780Reg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiAd5780Reg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiAd5780Reg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiAd5780Reg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiAd5780Reg.vhd.

◆ AxiAd5780Pkg

AxiAd5780Pkg
Package

Definition at line 25 of file AxiAd5780Reg.vhd.

The documentation for this class was generated from the following file: