SURF  1.0
Ad9249ReadoutGroup Entity Reference
+ Inheritance diagram for Ad9249ReadoutGroup:
+ Collaboration diagram for Ad9249ReadoutGroup:

Entities

rtl  architecture
 

Libraries

ieee 
UNISIM 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
vcomponents 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiStreamPkg  Package <AxiStreamPkg>
Ad9249Pkg  Package <Ad9249Pkg>

Generics

TPD_G  time := 1 ns
NUM_CHANNELS_G  natural range 1 to 8 := 8
IODELAY_GROUP_G  string := " DEFAULT_GROUP "
IDELAYCTRL_FREQ_G  real := 200 . 0
DEFAULT_DELAY_G  slv ( 4 downto 0 ) := ( others = > ' 0 ' )
ADC_INVERT_CH_G  slv ( 7 downto 0 ) := " 00000000 "

Ports

axilClk   in sl
axilRst   in sl
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
adcClkRst   in sl
adcSerial   in Ad9249SerialGroupType
adcStreamClk   in sl
adcStreams   out AxiStreamMasterArray ( NUM_CHANNELS_G - 1 downto 0 ) := ( others = > axiStreamMasterInit ( ( false , 2 , 8 , 0 , TKEEP_NORMAL_C , 0 , TUSER_NORMAL_C ) ) )

Detailed Description

See also
entity

Definition at line 36 of file Ad9249ReadoutGroup.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 38 of file Ad9249ReadoutGroup.vhd.

◆ NUM_CHANNELS_G

NUM_CHANNELS_G natural range 1 to 8 := 8
Generic

Definition at line 39 of file Ad9249ReadoutGroup.vhd.

◆ IODELAY_GROUP_G

IODELAY_GROUP_G string := " DEFAULT_GROUP "
Generic

Definition at line 40 of file Ad9249ReadoutGroup.vhd.

◆ IDELAYCTRL_FREQ_G

IDELAYCTRL_FREQ_G real := 200 . 0
Generic

Definition at line 41 of file Ad9249ReadoutGroup.vhd.

◆ DEFAULT_DELAY_G

DEFAULT_DELAY_G slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Generic

Definition at line 42 of file Ad9249ReadoutGroup.vhd.

◆ ADC_INVERT_CH_G

ADC_INVERT_CH_G slv ( 7 downto 0 ) := " 00000000 "
Generic

Definition at line 43 of file Ad9249ReadoutGroup.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 46 of file Ad9249ReadoutGroup.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 47 of file Ad9249ReadoutGroup.vhd.

◆ axilWriteMaster

Definition at line 50 of file Ad9249ReadoutGroup.vhd.

◆ axilWriteSlave

Definition at line 51 of file Ad9249ReadoutGroup.vhd.

◆ axilReadMaster

Definition at line 52 of file Ad9249ReadoutGroup.vhd.

◆ axilReadSlave

Definition at line 53 of file Ad9249ReadoutGroup.vhd.

◆ adcClkRst

adcClkRst in sl
Port

Definition at line 56 of file Ad9249ReadoutGroup.vhd.

◆ adcSerial

Definition at line 59 of file Ad9249ReadoutGroup.vhd.

◆ adcStreamClk

adcStreamClk in sl
Port

Definition at line 62 of file Ad9249ReadoutGroup.vhd.

◆ adcStreams

adcStreams out AxiStreamMasterArray ( NUM_CHANNELS_G - 1 downto 0 ) := ( others = > axiStreamMasterInit ( ( false , 2 , 8 , 0 , TKEEP_NORMAL_C , 0 , TUSER_NORMAL_C ) ) )
Port

Definition at line 64 of file Ad9249ReadoutGroup.vhd.

◆ ieee

ieee
Library

Definition at line 21 of file Ad9249ReadoutGroup.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 22 of file Ad9249ReadoutGroup.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 23 of file Ad9249ReadoutGroup.vhd.

◆ std_logic_unsigned

Definition at line 24 of file Ad9249ReadoutGroup.vhd.

◆ UNISIM

UNISIM
Library

Definition at line 26 of file Ad9249ReadoutGroup.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 27 of file Ad9249ReadoutGroup.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 29 of file Ad9249ReadoutGroup.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 30 of file Ad9249ReadoutGroup.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 31 of file Ad9249ReadoutGroup.vhd.

◆ Ad9249Pkg

Ad9249Pkg
Package

Definition at line 32 of file Ad9249ReadoutGroup.vhd.


The documentation for this class was generated from the following file: