SURF  1.0
XauiGtx7Core.vhd
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1 -------------------------------------------------------------------------------
2 -- File : XauiGtx7Core.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-02-12
5 -- Last update: 2016-02-19
6 -------------------------------------------------------------------------------
7 -- Description: 10 GigE XAUI for Gtx7
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 --! @see entity
22  --! @ingroup ethernet_XauiCore_gtx7
23 entity XauiGtx7Core is
24  port (
25  dclk : in std_logic;
26  reset : in std_logic;
27  clk156_out : out std_logic;
28  clk156_lock : out std_logic;
29  refclk : in std_logic;
30  xgmii_txd : in std_logic_vector(63 downto 0);
31  xgmii_txc : in std_logic_vector(7 downto 0);
32  xgmii_rxd : out std_logic_vector(63 downto 0);
33  xgmii_rxc : out std_logic_vector(7 downto 0);
34  xaui_tx_l0_p : out std_logic;
35  xaui_tx_l0_n : out std_logic;
36  xaui_tx_l1_p : out std_logic;
37  xaui_tx_l1_n : out std_logic;
38  xaui_tx_l2_p : out std_logic;
39  xaui_tx_l2_n : out std_logic;
40  xaui_tx_l3_p : out std_logic;
41  xaui_tx_l3_n : out std_logic;
42  xaui_rx_l0_p : in std_logic;
43  xaui_rx_l0_n : in std_logic;
44  xaui_rx_l1_p : in std_logic;
45  xaui_rx_l1_n : in std_logic;
46  xaui_rx_l2_p : in std_logic;
47  xaui_rx_l2_n : in std_logic;
48  xaui_rx_l3_p : in std_logic;
49  xaui_rx_l3_n : in std_logic;
50  signal_detect : in std_logic_vector(3 downto 0);
51  debug : out std_logic_vector(5 downto 0); -- Debug vector
52  configuration_vector : in std_logic_vector(6 downto 0);
53  status_vector : out std_logic_vector(7 downto 0)
54 );
55 end XauiGtx7Core;
56 
57 library xaui_v12_1;
58 use xaui_v12_1.all;
59 
60 architecture wrapper of XauiGtx7Core is
61 
62  component XauiGtx7Core_block is
63  port (
64  dclk : in std_logic;
65  reset : in std_logic;
66  clk156_out : out std_logic;
67  clk156_lock : out std_logic;
68  refclk : in std_logic;
69  xgmii_txd : in std_logic_vector(63 downto 0);
70  xgmii_txc : in std_logic_vector(7 downto 0);
71  xgmii_rxd : out std_logic_vector(63 downto 0);
72  xgmii_rxc : out std_logic_vector(7 downto 0);
73  xaui_tx_l0_p : out std_logic;
74  xaui_tx_l0_n : out std_logic;
75  xaui_tx_l1_p : out std_logic;
76  xaui_tx_l1_n : out std_logic;
77  xaui_tx_l2_p : out std_logic;
78  xaui_tx_l2_n : out std_logic;
79  xaui_tx_l3_p : out std_logic;
80  xaui_tx_l3_n : out std_logic;
81  xaui_rx_l0_p : in std_logic;
82  xaui_rx_l0_n : in std_logic;
83  xaui_rx_l1_p : in std_logic;
84  xaui_rx_l1_n : in std_logic;
85  xaui_rx_l2_p : in std_logic;
86  xaui_rx_l2_n : in std_logic;
87  xaui_rx_l3_p : in std_logic;
88  xaui_rx_l3_n : in std_logic;
89  signal_detect : in std_logic_vector(3 downto 0);
90  debug : out std_logic_vector(5 downto 0); -- Debug vector
91  -- GT Control Ports
92  -- DRP
93  gt0_drpaddr : in std_logic_vector(8 downto 0);
94  gt0_drpen : in std_logic;
95  gt0_drpdi : in std_logic_vector(15 downto 0);
96  gt0_drpdo : out std_logic_vector(15 downto 0);
97  gt0_drprdy : out std_logic;
98  gt0_drpwe : in std_logic;
99  -- TX Reset and Initialisation
100  gt0_txpmareset_in : in std_logic;
101  gt0_txpcsreset_in : in std_logic;
102  gt0_txresetdone_out : out std_logic;
103  -- RX Reset and Initialisation
104  gt0_rxpmareset_in : in std_logic;
105  gt0_rxpcsreset_in : in std_logic;
106  gt0_rxresetdone_out : out std_logic;
107  -- Clocking
108  gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
109  gt0_txphaligndone_out : out std_logic;
110  gt0_txphinitdone_out : out std_logic;
111  gt0_txdlysresetdone_out : out std_logic;
112  gt_qplllock_out : out std_logic;
113  -- Signal Integrity adn Functionality
114  -- Eye Scan
115  gt0_eyescantrigger_in : in std_logic;
116  gt0_eyescanreset_in : in std_logic;
117  gt0_eyescandataerror_out : out std_logic;
118  gt0_rxrate_in : in std_logic_vector(2 downto 0);
119  -- Loopback
120  gt0_loopback_in : in std_logic_vector(2 downto 0);
121  -- Polarity
122  gt0_rxpolarity_in : in std_logic;
123  gt0_txpolarity_in : in std_logic;
124  -- RX Decision Feedback Equalizer(DFE)
125  gt0_rxlpmen_in : in std_logic;
126  gt0_rxdfelpmreset_in : in std_logic;
127  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
128  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
129  -- TX Driver
130  gt0_txpostcursor_in : in std_logic_vector(4 downto 0);
131  gt0_txprecursor_in : in std_logic_vector(4 downto 0);
132  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
133  -- PRBS
134  gt0_rxprbscntreset_in : in std_logic;
135  gt0_rxprbserr_out : out std_logic;
136  gt0_rxprbssel_in : in std_logic_vector(2 downto 0);
137  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
138  gt0_txprbsforceerr_in : in std_logic;
139 
140  gt0_rxcdrhold_in : in std_logic;
141 
142  gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
143 
144  -- Status
145  gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
146  gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
147  gt0_rxcommadet_out : out std_logic;
148  -- DRP
149  gt1_drpaddr : in std_logic_vector(8 downto 0);
150  gt1_drpen : in std_logic;
151  gt1_drpdi : in std_logic_vector(15 downto 0);
152  gt1_drpdo : out std_logic_vector(15 downto 0);
153  gt1_drprdy : out std_logic;
154  gt1_drpwe : in std_logic;
155  -- TX Reset and Initialisation
156  gt1_txpmareset_in : in std_logic;
157  gt1_txpcsreset_in : in std_logic;
158  gt1_txresetdone_out : out std_logic;
159  -- RX Reset and Initialisation
160  gt1_rxpmareset_in : in std_logic;
161  gt1_rxpcsreset_in : in std_logic;
162  gt1_rxresetdone_out : out std_logic;
163  -- Clocking
164  gt1_rxbufstatus_out : out std_logic_vector(2 downto 0);
165  gt1_txphaligndone_out : out std_logic;
166  gt1_txphinitdone_out : out std_logic;
167  gt1_txdlysresetdone_out : out std_logic;
168  -- Signal Integrity adn Functionality
169  -- Eye Scan
170  gt1_eyescantrigger_in : in std_logic;
171  gt1_eyescanreset_in : in std_logic;
172  gt1_eyescandataerror_out : out std_logic;
173  gt1_rxrate_in : in std_logic_vector(2 downto 0);
174  -- Loopback
175  gt1_loopback_in : in std_logic_vector(2 downto 0);
176  -- Polarity
177  gt1_rxpolarity_in : in std_logic;
178  gt1_txpolarity_in : in std_logic;
179  -- RX Decision Feedback Equalizer(DFE)
180  gt1_rxlpmen_in : in std_logic;
181  gt1_rxdfelpmreset_in : in std_logic;
182  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
183  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
184  -- TX Driver
185  gt1_txpostcursor_in : in std_logic_vector(4 downto 0);
186  gt1_txprecursor_in : in std_logic_vector(4 downto 0);
187  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
188  -- PRBS
189  gt1_rxprbscntreset_in : in std_logic;
190  gt1_rxprbserr_out : out std_logic;
191  gt1_rxprbssel_in : in std_logic_vector(2 downto 0);
192  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
193  gt1_txprbsforceerr_in : in std_logic;
194 
195  gt1_rxcdrhold_in : in std_logic;
196 
197  gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
198 
199  -- Status
200  gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
201  gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
202  gt1_rxcommadet_out : out std_logic;
203  -- DRP
204  gt2_drpaddr : in std_logic_vector(8 downto 0);
205  gt2_drpen : in std_logic;
206  gt2_drpdi : in std_logic_vector(15 downto 0);
207  gt2_drpdo : out std_logic_vector(15 downto 0);
208  gt2_drprdy : out std_logic;
209  gt2_drpwe : in std_logic;
210  -- TX Reset and Initialisation
211  gt2_txpmareset_in : in std_logic;
212  gt2_txpcsreset_in : in std_logic;
213  gt2_txresetdone_out : out std_logic;
214  -- RX Reset and Initialisation
215  gt2_rxpmareset_in : in std_logic;
216  gt2_rxpcsreset_in : in std_logic;
217  gt2_rxresetdone_out : out std_logic;
218  -- Clocking
219  gt2_rxbufstatus_out : out std_logic_vector(2 downto 0);
220  gt2_txphaligndone_out : out std_logic;
221  gt2_txphinitdone_out : out std_logic;
222  gt2_txdlysresetdone_out : out std_logic;
223  -- Signal Integrity adn Functionality
224  -- Eye Scan
225  gt2_eyescantrigger_in : in std_logic;
226  gt2_eyescanreset_in : in std_logic;
227  gt2_eyescandataerror_out : out std_logic;
228  gt2_rxrate_in : in std_logic_vector(2 downto 0);
229  -- Loopback
230  gt2_loopback_in : in std_logic_vector(2 downto 0);
231  -- Polarity
232  gt2_rxpolarity_in : in std_logic;
233  gt2_txpolarity_in : in std_logic;
234  -- RX Decision Feedback Equalizer(DFE)
235  gt2_rxlpmen_in : in std_logic;
236  gt2_rxdfelpmreset_in : in std_logic;
237  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
238  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
239  -- TX Driver
240  gt2_txpostcursor_in : in std_logic_vector(4 downto 0);
241  gt2_txprecursor_in : in std_logic_vector(4 downto 0);
242  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
243  -- PRBS
244  gt2_rxprbscntreset_in : in std_logic;
245  gt2_rxprbserr_out : out std_logic;
246  gt2_rxprbssel_in : in std_logic_vector(2 downto 0);
247  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
248  gt2_txprbsforceerr_in : in std_logic;
249 
250  gt2_rxcdrhold_in : in std_logic;
251 
252  gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
253 
254  -- Status
255  gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
256  gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
257  gt2_rxcommadet_out : out std_logic;
258  -- DRP
259  gt3_drpaddr : in std_logic_vector(8 downto 0);
260  gt3_drpen : in std_logic;
261  gt3_drpdi : in std_logic_vector(15 downto 0);
262  gt3_drpdo : out std_logic_vector(15 downto 0);
263  gt3_drprdy : out std_logic;
264  gt3_drpwe : in std_logic;
265  -- TX Reset and Initialisation
266  gt3_txpmareset_in : in std_logic;
267  gt3_txpcsreset_in : in std_logic;
268  gt3_txresetdone_out : out std_logic;
269  -- RX Reset and Initialisation
270  gt3_rxpmareset_in : in std_logic;
271  gt3_rxpcsreset_in : in std_logic;
272  gt3_rxresetdone_out : out std_logic;
273  -- Clocking
274  gt3_rxbufstatus_out : out std_logic_vector(2 downto 0);
275  gt3_txphaligndone_out : out std_logic;
276  gt3_txphinitdone_out : out std_logic;
277  gt3_txdlysresetdone_out : out std_logic;
278  -- Signal Integrity adn Functionality
279  -- Eye Scan
280  gt3_eyescantrigger_in : in std_logic;
281  gt3_eyescanreset_in : in std_logic;
282  gt3_eyescandataerror_out : out std_logic;
283  gt3_rxrate_in : in std_logic_vector(2 downto 0);
284  -- Loopback
285  gt3_loopback_in : in std_logic_vector(2 downto 0);
286  -- Polarity
287  gt3_rxpolarity_in : in std_logic;
288  gt3_txpolarity_in : in std_logic;
289  -- RX Decision Feedback Equalizer(DFE)
290  gt3_rxlpmen_in : in std_logic;
291  gt3_rxdfelpmreset_in : in std_logic;
292  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
293  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
294  -- TX Driver
295  gt3_txpostcursor_in : in std_logic_vector(4 downto 0);
296  gt3_txprecursor_in : in std_logic_vector(4 downto 0);
297  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
298  -- PRBS
299  gt3_rxprbscntreset_in : in std_logic;
300  gt3_rxprbserr_out : out std_logic;
301  gt3_rxprbssel_in : in std_logic_vector(2 downto 0);
302  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
303  gt3_txprbsforceerr_in : in std_logic;
304 
305  gt3_rxcdrhold_in : in std_logic;
306 
307  gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
308 
309  -- Status
310  gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
311  gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
312  gt3_rxcommadet_out : out std_logic;
313  configuration_vector : in std_logic_vector(6 downto 0);
314  status_vector : out std_logic_vector(7 downto 0)
315 );
316  end component;
317 
318  ATTRIBUTE CORE_GENERATION_INFO : STRING;
319  ATTRIBUTE CORE_GENERATION_INFO OF wrapper : ARCHITECTURE IS "XauiGtx7Core,xaui_v12_1,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xaui,x_ipVersion=12.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,c_family=kintex7,c_component_name=XauiGtx7Core,c_is_dxaui=false,c_has_mdio=false,c_sub_core_name=XauiGtx7Core_gt,c_gt_dmonitorout_width=8,c_gt_txdiffctrl_width=16}";
320  ATTRIBUTE X_CORE_INFO : STRING;
321  ATTRIBUTE X_CORE_INFO OF wrapper: ARCHITECTURE IS "xaui_v12_1,Vivado 2014.4.1";
322 
323 begin
324 
325  U0 : XauiGtx7Core_block
326  port map(
327  dclk => dclk,
328  reset => reset,
329  clk156_out => clk156_out,
330  clk156_lock => clk156_lock,
331  refclk => refclk,
332  xgmii_txd => xgmii_txd,
333  xgmii_txc => xgmii_txc,
334  xgmii_rxd => xgmii_rxd,
335  xgmii_rxc => xgmii_rxc,
336  xaui_tx_l0_p => xaui_tx_l0_p,
337  xaui_tx_l0_n => xaui_tx_l0_n,
338  xaui_tx_l1_p => xaui_tx_l1_p,
339  xaui_tx_l1_n => xaui_tx_l1_n,
340  xaui_tx_l2_p => xaui_tx_l2_p,
341  xaui_tx_l2_n => xaui_tx_l2_n,
342  xaui_tx_l3_p => xaui_tx_l3_p,
343  xaui_tx_l3_n => xaui_tx_l3_n,
344  xaui_rx_l0_p => xaui_rx_l0_p,
345  xaui_rx_l0_n => xaui_rx_l0_n,
346  xaui_rx_l1_p => xaui_rx_l1_p,
347  xaui_rx_l1_n => xaui_rx_l1_n,
348  xaui_rx_l2_p => xaui_rx_l2_p,
349  xaui_rx_l2_n => xaui_rx_l2_n,
350  xaui_rx_l3_p => xaui_rx_l3_p,
351  xaui_rx_l3_n => xaui_rx_l3_n,
352  signal_detect => signal_detect,
353  debug => debug,
354  -- DRP
355  gt0_drpaddr => (others => '0'),
356  gt0_drpen => '0',
357  gt0_drpdi => (others => '0'),
358  gt0_drpdo => open,
359  gt0_drprdy => open,
360  gt0_drpwe => '0',
361  -- TX Reset and Initialisation
362  gt0_txpmareset_in => '0',
363  gt0_txpcsreset_in => '0',
364  gt0_txresetdone_out => open,
365  -- RX Reset and Initialisation
366  gt0_rxpmareset_in => '0',
367  gt0_rxpcsreset_in => '0',
368  gt0_rxresetdone_out => open,
369  -- Clocking
370  gt0_rxbufstatus_out => open,
371  gt0_txphaligndone_out => open,
372  gt0_txphinitdone_out => open,
373  gt0_txdlysresetdone_out => open,
374  gt_qplllock_out => open,
375  -- Signal Integrity adn Functionality
376  -- Eye Scan
377  gt0_eyescantrigger_in => '0',
378  gt0_eyescanreset_in => '0',
379  gt0_eyescandataerror_out => open,
380  gt0_rxrate_in => "000",
381  -- Loopback
382  gt0_loopback_in => "000",
383  -- Polarity
384  gt0_rxpolarity_in => '0',
385  gt0_txpolarity_in => '0',
386  -- RX Decision Feedback Equalizer(DFE)
387  gt0_rxlpmen_in => '0',
388  gt0_rxdfelpmreset_in => '0',
389  gt0_rxmonitorsel_in => "00",
390  gt0_rxmonitorout_out => open,
391  -- TX Driver
392  gt0_txdiffctrl_in => "1000",
393  gt0_txpostcursor_in => "00000",
394  gt0_txprecursor_in => "00000",
395  -- PRBS - GT
396  gt0_rxprbscntreset_in => '0',
397  gt0_rxprbserr_out => open,
398  gt0_rxprbssel_in => "000",
399  gt0_txprbssel_in => "000",
400  gt0_txprbsforceerr_in => '0',
401 
402  gt0_rxcdrhold_in => '0',
403 
404  gt0_dmonitorout_out => open,
405 
406  -- Status
407  gt0_rxdisperr_out => open,
408  gt0_rxnotintable_out => open,
409  gt0_rxcommadet_out => open,
410  -- DRP
411  gt1_drpaddr => (others => '0'),
412  gt1_drpen => '0',
413  gt1_drpdi => (others => '0'),
414  gt1_drpdo => open,
415  gt1_drprdy => open,
416  gt1_drpwe => '0',
417  -- TX Reset and Initialisation
418  gt1_txpmareset_in => '0',
419  gt1_txpcsreset_in => '0',
420  gt1_txresetdone_out => open,
421  -- RX Reset and Initialisation
422  gt1_rxpmareset_in => '0',
423  gt1_rxpcsreset_in => '0',
424  gt1_rxresetdone_out => open,
425  -- Clocking
426  gt1_rxbufstatus_out => open,
427  gt1_txphaligndone_out => open,
428  gt1_txphinitdone_out => open,
429  gt1_txdlysresetdone_out => open,
430  -- Signal Integrity adn Functionality
431  -- Eye Scan
432  gt1_eyescantrigger_in => '0',
433  gt1_eyescanreset_in => '0',
434  gt1_eyescandataerror_out => open,
435  gt1_rxrate_in => "000",
436  -- Loopback
437  gt1_loopback_in => "000",
438  -- Polarity
439  gt1_rxpolarity_in => '0',
440  gt1_txpolarity_in => '0',
441  -- RX Decision Feedback Equalizer(DFE)
442  gt1_rxlpmen_in => '0',
443  gt1_rxdfelpmreset_in => '0',
444  gt1_rxmonitorsel_in => "00",
445  gt1_rxmonitorout_out => open,
446  -- TX Driver
447  gt1_txdiffctrl_in => "1000",
448  gt1_txpostcursor_in => "00000",
449  gt1_txprecursor_in => "00000",
450  -- PRBS - GT
451  gt1_rxprbscntreset_in => '0',
452  gt1_rxprbserr_out => open,
453  gt1_rxprbssel_in => "000",
454  gt1_txprbssel_in => "000",
455  gt1_txprbsforceerr_in => '0',
456 
457  gt1_rxcdrhold_in => '0',
458 
459  gt1_dmonitorout_out => open,
460 
461  -- Status
462  gt1_rxdisperr_out => open,
463  gt1_rxnotintable_out => open,
464  gt1_rxcommadet_out => open,
465  -- DRP
466  gt2_drpaddr => (others => '0'),
467  gt2_drpen => '0',
468  gt2_drpdi => (others => '0'),
469  gt2_drpdo => open,
470  gt2_drprdy => open,
471  gt2_drpwe => '0',
472  -- TX Reset and Initialisation
473  gt2_txpmareset_in => '0',
474  gt2_txpcsreset_in => '0',
475  gt2_txresetdone_out => open,
476  -- RX Reset and Initialisation
477  gt2_rxpmareset_in => '0',
478  gt2_rxpcsreset_in => '0',
479  gt2_rxresetdone_out => open,
480  -- Clocking
481  gt2_rxbufstatus_out => open,
482  gt2_txphaligndone_out => open,
483  gt2_txphinitdone_out => open,
484  gt2_txdlysresetdone_out => open,
485  -- Signal Integrity adn Functionality
486  -- Eye Scan
487  gt2_eyescantrigger_in => '0',
488  gt2_eyescanreset_in => '0',
489  gt2_eyescandataerror_out => open,
490  gt2_rxrate_in => "000",
491  -- Loopback
492  gt2_loopback_in => "000",
493  -- Polarity
494  gt2_rxpolarity_in => '0',
495  gt2_txpolarity_in => '0',
496  -- RX Decision Feedback Equalizer(DFE)
497  gt2_rxlpmen_in => '0',
498  gt2_rxdfelpmreset_in => '0',
499  gt2_rxmonitorsel_in => "00",
500  gt2_rxmonitorout_out => open,
501  -- TX Driver
502  gt2_txdiffctrl_in => "1000",
503  gt2_txpostcursor_in => "00000",
504  gt2_txprecursor_in => "00000",
505  -- PRBS - GT
506  gt2_rxprbscntreset_in => '0',
507  gt2_rxprbserr_out => open,
508  gt2_rxprbssel_in => "000",
509  gt2_txprbssel_in => "000",
510  gt2_txprbsforceerr_in => '0',
511 
512  gt2_rxcdrhold_in => '0',
513 
514  gt2_dmonitorout_out => open,
515 
516  -- Status
517  gt2_rxdisperr_out => open,
518  gt2_rxnotintable_out => open,
519  gt2_rxcommadet_out => open,
520  -- DRP
521  gt3_drpaddr => (others => '0'),
522  gt3_drpen => '0',
523  gt3_drpdi => (others => '0'),
524  gt3_drpdo => open,
525  gt3_drprdy => open,
526  gt3_drpwe => '0',
527  -- TX Reset and Initialisation
528  gt3_txpmareset_in => '0',
529  gt3_txpcsreset_in => '0',
530  gt3_txresetdone_out => open,
531  -- RX Reset and Initialisation
532  gt3_rxpmareset_in => '0',
533  gt3_rxpcsreset_in => '0',
534  gt3_rxresetdone_out => open,
535  -- Clocking
536  gt3_rxbufstatus_out => open,
537  gt3_txphaligndone_out => open,
538  gt3_txphinitdone_out => open,
539  gt3_txdlysresetdone_out => open,
540  -- Signal Integrity adn Functionality
541  -- Eye Scan
542  gt3_eyescantrigger_in => '0',
543  gt3_eyescanreset_in => '0',
544  gt3_eyescandataerror_out => open,
545  gt3_rxrate_in => "000",
546  -- Loopback
547  gt3_loopback_in => "000",
548  -- Polarity
549  gt3_rxpolarity_in => '0',
550  gt3_txpolarity_in => '0',
551  -- RX Decision Feedback Equalizer(DFE)
552  gt3_rxlpmen_in => '0',
553  gt3_rxdfelpmreset_in => '0',
554  gt3_rxmonitorsel_in => "00",
555  gt3_rxmonitorout_out => open,
556  -- TX Driver
557  gt3_txdiffctrl_in => "1000",
558  gt3_txpostcursor_in => "00000",
559  gt3_txprecursor_in => "00000",
560  -- PRBS - GT
561  gt3_rxprbscntreset_in => '0',
562  gt3_rxprbserr_out => open,
563  gt3_rxprbssel_in => "000",
564  gt3_txprbssel_in => "000",
565  gt3_txprbsforceerr_in => '0',
566 
567  gt3_rxcdrhold_in => '0',
568 
569  gt3_dmonitorout_out => open,
570 
571  -- Status
572  gt3_rxdisperr_out => open,
573  gt3_rxnotintable_out => open,
574  gt3_rxcommadet_out => open,
575  configuration_vector => configuration_vector,
576  status_vector => status_vector
577 );
578 
579 end wrapper;
XauiGtx7Core.xaui_rx_l1_n
in xaui_rx_l1_nstd_logic
Definition: XauiGtx7Core.vhd:45
XauiGtx7Core.reset
in resetstd_logic
Definition: XauiGtx7Core.vhd:26
XauiGtx7Core.xaui_tx_l1_p
out xaui_tx_l1_pstd_logic
Definition: XauiGtx7Core.vhd:36
XauiGtx7Core.xaui_tx_l0_p
out xaui_tx_l0_pstd_logic
Definition: XauiGtx7Core.vhd:34
XauiGtx7Core.xaui_tx_l2_p
out xaui_tx_l2_pstd_logic
Definition: XauiGtx7Core.vhd:38
XauiGtx7Core.xaui_rx_l3_n
in xaui_rx_l3_nstd_logic
Definition: XauiGtx7Core.vhd:49
XauiGtx7Core.refclk
in refclkstd_logic
Definition: XauiGtx7Core.vhd:29
XauiGtx7Core.clk156_lock
out clk156_lockstd_logic
Definition: XauiGtx7Core.vhd:28
XauiGtx7Core.xaui_tx_l0_n
out xaui_tx_l0_nstd_logic
Definition: XauiGtx7Core.vhd:35
XauiGtx7Core.signal_detect
in signal_detectstd_logic_vector( 3 downto 0)
Definition: XauiGtx7Core.vhd:50
XauiGtx7Core.xaui_rx_l0_n
in xaui_rx_l0_nstd_logic
Definition: XauiGtx7Core.vhd:43
XauiGtx7Core.clk156_out
out clk156_outstd_logic
Definition: XauiGtx7Core.vhd:27
XauiGtx7Core.xaui_tx_l3_n
out xaui_tx_l3_nstd_logic
Definition: XauiGtx7Core.vhd:41
XauiGtx7Core.xgmii_txd
in xgmii_txdstd_logic_vector( 63 downto 0)
Definition: XauiGtx7Core.vhd:30
XauiGtx7Core.xaui_tx_l1_n
out xaui_tx_l1_nstd_logic
Definition: XauiGtx7Core.vhd:37
XauiGtx7Core.xaui_rx_l2_p
in xaui_rx_l2_pstd_logic
Definition: XauiGtx7Core.vhd:46
XauiGtx7Core.xgmii_rxc
out xgmii_rxcstd_logic_vector( 7 downto 0)
Definition: XauiGtx7Core.vhd:33
XauiGtx7Core.status_vector
out status_vectorstd_logic_vector( 7 downto 0)
Definition: XauiGtx7Core.vhd:54
XauiGtx7Core.xaui_tx_l3_p
out xaui_tx_l3_pstd_logic
Definition: XauiGtx7Core.vhd:40
XauiGtx7Core.xaui_rx_l1_p
in xaui_rx_l1_pstd_logic
Definition: XauiGtx7Core.vhd:44
XauiGtx7Core.dclk
in dclkstd_logic
Definition: XauiGtx7Core.vhd:25
XauiGtx7.ieee
_library_ ieeeieee
Definition: XauiGtx7.vhd:18
XauiGtx7Core.xaui_rx_l2_n
in xaui_rx_l2_nstd_logic
Definition: XauiGtx7Core.vhd:47
XauiGtx7Core.xaui_rx_l3_p
in xaui_rx_l3_pstd_logic
Definition: XauiGtx7Core.vhd:48
XauiGtx7Core.configuration_vector
in configuration_vectorstd_logic_vector( 6 downto 0)
Definition: XauiGtx7Core.vhd:52
XauiGtx7Core.xaui_rx_l0_p
in xaui_rx_l0_pstd_logic
Definition: XauiGtx7Core.vhd:42
XauiGtx7Core.xgmii_txc
in xgmii_txcstd_logic_vector( 7 downto 0)
Definition: XauiGtx7Core.vhd:31
XauiGtx7Core.xaui_tx_l2_n
out xaui_tx_l2_nstd_logic
Definition: XauiGtx7Core.vhd:39
XauiGtx7Core.debug
out debugstd_logic_vector( 5 downto 0)
Definition: XauiGtx7Core.vhd:51
XauiGtx7Core.xgmii_rxd
out xgmii_rxdstd_logic_vector( 63 downto 0)
Definition: XauiGtx7Core.vhd:32