Welcome to pix2pgp’s documentation!
This is currently a work in progress. New documentation is being added incrementally over time.
Pix2PGP is a full-stack, highly-configurable data acquisition framework designed to support front-end detector Application-Specific Integrated Circuits (ASICs) that operate on a sparse readout scheme. It provides:
An ASIC RTL core that receives sparse hit data from multiple sources and performs event building given externally-driven frame delimiters
An FPGA firmware receiver that aggregates the ASIC-generated data lanes into a single consolidated event frame
A Python software decoding suite for parsing the aggregated frames into an easily-accessible format
Contents:
- Introduction
- Setup
- Architecture
- HowTos
- How to Import Pix2PGP Sources in Your Project
- How to Integrate the Pix2PGP Core in Your ASIC
- How to Integrate the Pix2PGP FPGA Receiver in Your FPGA
- How to Perform VHDL Syntax Checks with GHDL
- How to Simulate Using GHDL
- How to Simulate Using VCS
- How to Decode Pix2PGP Data with the Parser
- How to Use Pix2PgpSparseProcessor with Rogue
- How to Add Support for a New ASIC
- How to Benchmark Throughput and Latency
Please email cbakalis@slac.stanford.edu if you see any errors or have any questions about anything in the current documentation.