Architecture

This section describes the internal architecture of Pix2PGP. It covers the ASIC-side core (Column Manager / Column Supervisor / Arbiter), the FPGA receiver (LaneRx / Lane Supervisor / Lane Merger / Trigger Manager), the data frame format, and per-ASIC parameterization.

Architecture:

• Top-Level Overview
• ASIC Core Architecture
• Data-Flow and Corner Cases
• FPGA Receiver Architecture
• Data Frame Format
• ASIC Implementations