axi-soc-ultra-plus-core Documentation

AXI-Lite/AXI-Stream interconnect, DMA, and RFSoC platform library for SLAC SoC carrier designs, used as a git submodule by downstream firmware projects.

Contents:

• Tutorial
  • First SoC Bring-up
• How-To Guides
  • Install Rogue
  • Launch the Rogue GUI
  • Remote Bitstream Update
  • SD Card Imaging
  • Change Boot Mode via XSCT
  • Program Flash Memory
• Reference
  • Supported Boards
  • PyRogue API Reference
  • Register Map
• Explanation
  • Platform Architecture