Reference
=========

This section is the lookup reference for ``axi-pcie-core``: RTL entity ports
and generics, the BAR0 register address map, PyRogue class signatures, and
the supported-board catalogue.  Unlike the :doc:`/explanation/index` section,
these pages are designed for scanning, not reading start-to-finish.

.. toctree::
   :maxdepth: 2
   :caption: Reference

   rtl_entities
   register_map
   pyrogue_api
   supported_boards